Research Achievements / 業績一覧

If you are interested in all the published articles, please visit https://trios.tsukuba.ac.jp/en/researcher/0000000912

• Xiaofan Liu, Kai Sheng, Yoshiki Yamaguchi, Yongfang Xie, Yunyi Yan, and Ye Tao, "An adaptive finite-time formation control against actuator attacks in nonlinear singular multiagent systems", in Nonlinear Dynamics, (2025). pp.1-14, doi:10.1007/s11071-025-10970-2

• K. Wei, H. Amano, R. Niwase, Y. Yamaguchi, and T. Miyoshi, "Qu-Trefoil: Large-scale Quantum Circuit Simulator Working on FPGA with SATA Storages," in IEEE Transactions on Computers, Vol., No.1, pp.1-16, PrePrints 5555, doi:10.1109/TC.2024.3521546.

• I. Firmansyah, B. Setiadi, A. Subekti, H. Nugraha, E. Kurniawan, and Y. Yamaguchi, "Enhancing IoT data acquisition efficiency via FPGA-based implementation with OpenCL framework," Computers and Electrical Engineering, Volume 120, Part C, 2024, Article #109830, ISSN 0045-7906, doi:10.1016/j.compeleceng.2024.109830.

• Y. Oshima, Y. Yamaguchi, R. Tsugami, T. Fujiwara, T. Fukui and S. Narikawa, "FPGA-Based Improved Background Subtraction for Ultra-Low Latency," in IEEE Access, vol. 12, pp. 164063-164080, 2024, doi: 10.1109/ACCESS.2024.3483548.

• I. Firmansyah, Y. Yamaguchi, T. Maruyama, Y. Matsuura, Z. Heming, S. Kawai, H. Nobuhara, "FPGA-based stereo matching for crop height measurement using monocular camera," Microprocessors and Microsystems, Volume 108, Article #105063, 19 pages, July 2024, ISSN 0141-9331, doi:10.1016/j.micpro.2024.105063.

• Riadh Ben Abdelhamid, Yoshiki Yamaguchi, and Taisuke Boku, “A scalable many-core overlay architecture on an HBM2-enabled multi-die FPGA,” ACM Transactions on Reconfigurable Technology and Systems, p.1-34, July 2022. doi: 10.1145/3547657

• Firmansyah, Iman; Yamaguchi, Yoshiki, ``Real-Time FPGA Implementation of FIR Filter Using OpenCL Design", Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, pp.1-13, doi: 10.1007/s11265-021-01723-6, 2022.

• 花田信子, 三井雅史, 志築文太郎, 山口佳樹, 橋本悠希, “電子回路利用に向けた漆膜の電気絶縁特性評価”, 計測自動制御学会論文集, 58 巻, 1 号, pp.61-71, doi:10.9746/sicetr.58.61, 2022.

• Riadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku, ``A highly-efficient and tightly-connected many-core overlay architecture'',  IEEE Access, Volume 9, pp.65277-65292, doi: 10.1109/ACCESS.2021.3074171, 2021.

• Iman Firmansyah and Yoshiki Yamaguchi, ``FPGA-based implementation of a chirp signal generator using an OpenCL design'', Microprocessors and Microsystems, Vol.77, Article 103199, pp.1-8, doi: 10.1016/j.micpro.2020.103199, 2020.

• Changdao Du and Yoshiki Yamaguchi, ``High-Level Synthesis Design for Stencil Computations on FPGA with High Bandwidth Memory'', Electronics, Vol.9, No.8, Article 1275, pp.1-19, doi: 10.3390/electronics9081275, 2020.

• Ryohei Kobayashi, Norihisa Fujita, Yoshiki Yamaguchi, Taisuke Boku, Kohji Yoshikawa, Makito Abe, Masayuki Umemura, ``Multi-Hybrid Accelerated Simulation by GPU and FPGA on Radiative Transfer Simulation in Astrophysics'', Journal of Information Processing (Special Section on Advanced Computing Systems, ACS), Vol.28, pp.1073-1089, doi: 10.2197/ipsjjip.28.1073, 2020.

• 藤田典久, 小林諒平, 山口佳樹, 上野知洋, 佐野健太郎, 朴泰祐,``OpenCLプログラミングを用いた並列FPGA処理システムの性能評価'', 情報処理学会論文誌コンピューティングシステム（ACS）,Vol.13, No.3, pp.13-28, ISSN: 1882-7829, 2020.

• 長岡佑治, 牛若光太, 山口佳樹,``高信頼な車両間映像転送をWi-Fi ベースで支援するマイクロ秒レベルストリーミング処理ハードウェア'', 自動車技術会論文集,Vol.51, No.3, pp.503-508, doi: 10.11351/jsaeronbun.51.503, 2020．

• 藤田典久, 小林諒平, 山口佳樹, 朴泰祐, 吉川耕司, 安部牧人, 梅村雅之, ``宇宙輻射輸送コードにおけるOpenCLによるFPGA演算加速最適化'', 情報処理学会論文誌コンピューティングシステム（ACS）, Vol.12, No.3, pp.64-75, ISSN: 1882-7829, 2019.

• Iman Firmansyah and Yoshiki Yamaguchi, ``OpenCL Implementation of FPGA-based Signal Generation and Measurement'', IEEE Access, Volume 7, pp.48849-48859, doi: 10.1109/ACCESS.2019.2910391, 2019.

• 丸山裕士, 山口佳樹, 児玉祐悦, ``FPGA によるブレ補正機構に関する研究'', 電子情報通信学会論文誌,D分冊, Vol.J99-D, No.6, pp.594-606, doi: 10.14923/transinfj.2015JDP7029, 2016．

• Kei Kinoshita, Yoshiki Yamaguchi, Daisuke Takano, Tomoyuki Okamura, and Tetsuhiko Yao, ``Energy Efficiency Improvement by Dynamic Reconfiguration for Embedded Systems'', IEICE TRANSACTIONS on Information and Systems, Vol.E98-D, No.2, pp.220-229, doi: 10.1587/transinf.2014RCP0015, 2015.

• Suguru Ochiai, Toru Yabuki, Yoshiki Yamaguchi and Yuetsu Kodama, ``Game-Tree Simplification by Pattern Matching and Its Acceleration Approach using an FPGA'', International Journal of Computer, Electrical, Automation, Control and Information Engineering,Vol.7, No.2, pp.237-242, doi: 10.5281/zenodo.1084226, 2013.

• Kei Kinoshita, Daisuke Takano, Tomoyuki Okamura, Tetsuhiko Yao, and Yoshiki Yamaguchi, ``An augmented reality system with a coarse-grained reconfigurable device", ACM SIGARCH Computer Architecture News, Vol.40, Issue 5, pp.16-21, doi: 10.1145/2460216.2460220, 2012.

• Shoji Tanabe, Takuya Nagashima, and Yoshiki Yamaguchi, ``A Study of FPGA-based Flexible SIMD Processor", ACM SIGARCH Computer Architecture News, Vol.39, Issue 4, pp.86-89, doi: 10.1145/2082156.2082179, 2011.

• Moritoshi Yasunaga, Noriyuki Aibe, Yoshiki Yamaguchi, Yorihisa Yamamoto, Takaaki Awano, and Ikuo Yoshihara, ``Real-world applications on the reconfigurable-VLSI-based double-lens tracking-camera'', Journal of Artificial Life and Robotics,Vol.13, No.1,pp.73-76, doi: 10.1007/s10015-008-0517-5, 2008.

• Moritoshi Yasunaga, Noriyuki Aibe, Yoshiki Yamaguchi, Yorihisa Yamamoto, Takaaki Awano and Ikuo Yoshihara, ``A Reconfigurable-VLSI-based Double-lens Tracking-camera'', Journal of Artificial Life and Robotics,Vol.12, No.1-2,pp.219-222, doi: 10.1007/s10015-007-0470-8, 2008.

• Shingo Masuno, Tsutomu Maruyama, Yoshiki Yamaguchi, and Akihiko Konagaya, ``Multiple Sequence Alignment Based on Dynamic Programming using FPGA, ``IEICE Transactions on Information and Systems'', Vol.E90-D, No.12, doi: 10.1093/ietisy/e90-d.12.1939, pp.1939-1946, 2007.

• Yoshiki Yamaguchi, Tsutomu Maruyama, Ryuzo Azuma, Moritoshi Yasunaga, and Akihiko Konagaya, ``Mesoscopic-level simulation of dynamics and interactions of biological molecules using Monte Carlo simulation'', Journal of VLSI Signal Processing Systems, Vol.48, No.3,pp.287-299, doi: 10.1007/s11265-007-0072-7, 2007.

• Yoshiki Yamaguchi, Moritoshi Yasunaga, Kazuya Hayashi, Noriyuki Aibe, Yorihisa Yamamoto, and Ikuo Yoshihara, ``A Bio-inspired Tracking-camera System'', Journal of Artificial Life and Robotics, Vol.11, No.14,pp.128-134, doi: 10.1007/s10015-006-0414-8, 2007.

• 山口佳樹, 宮島洋介, 丸山勉, 小長谷明彦, ``書き換え可能ハードウェアを用いた高速ホモロジー検索システム", 情報処理学会論文誌, Vol.43, No.SIG6 (HPS5), pp.196-205, ISSN: 0387-5806, 2002.

• 山口佳樹, 山内敦, 丸山勉, 星野力, ``ジレンマゲームにおける価値観の発生とその解析", 計測自動制御学会論文誌, Vol.38, No.3, pp.299-308, doi: doi.org/10.9746/sicetr1965.38.299, 2002．

• 丸山勉, 船津輝宣, 関峰伸, 山口佳樹, 星野力, ``Field-Programmable Gate-Arrayによる進化的計算の高速化", 情報処理学会論文誌, Vol.40, No.5, pp.2132-2141, ISSN: 1882-7764, 1999.

• T. Yokono and Y. Yamaguchi, "Accelerating CRS Format Conversion for Sparse Matrix Computation with an FPGA," 2025 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Milano, Italy, 2025, pp. 1-1, doi: 10.1109/IPDPSW-----.2025.-----.

• J. Li, L. Ao, K. Sheng, and Y. Yamaguchi, "A Method of Detecting Port Bay Numbers and Optimizing Effects Under Various Weather Scenarios," In Proceedings of the 43rd IEEE International Conference on Consumer Electronics (ICCE), IEEE, Las Vegas NV, USA, 2025, pp.1-4, doi: 10.1109/ICCE63647.2025.10930172.

• D. Tabata, T. Kobori, Y. Yamaguchi, R. Tsugami, T. Fujiwara, T. Fukui, and S. Narikawa, "Low-latency immersive display systems with FPGA for remote applications," In Proceedings of the IEEE Consumer Communications and Networking Conference (IEEE CCNC), IEEE, Las Vegas NV, USA, 2025, 2 pages, doi: ---.

• Y. Tan, M. Nishimura, R.B. Abdelhamid, B. Guo, Q. Gao, and Y. Yamaguchi, "Systolic Array-Based Many-Core Processor with Simultaneous Dual-Instruction Issuance," In Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART '24), Association for Computing Machinery, New York, NY, USA, 2024, pp.119–125, doi:10.1145/3665283.3665298

• K. Wei, H. Amano, R. Niwase, and Y. Yamaguchi, "A data compressor for FPGA-based state vector quantum simulators," In Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART '24), Association for Computing Machinery, New York, NY, USA, 2024, pp.63–70, doi:10.1145/3665283.3665293

• Y. Tan, R. B. Abdelhamid, B. Guo, Q. Gao, M. Nishimura and Y. Yamaguchi, "Scalable dual-instruction multiple-data processing on an efficient systolic-array architecture," 2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), San Francisco, CA, USA, 2024, pp. 1-1, doi: 10.1109/IPDPSW63119.2024.00048.

• R. Nakagawa, Y. Yamaguchi, H. Nobuhara, I. Firmansyah and K. Sheng, "Stereo Vision System for Crop Height Measurement Using a Monocular Camera-Equipped Drone," 2024 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, USA, 2024, pp. 1-2, doi: 10.1109/ICCE59016.2024.10444287.

• Y. Oshima, Y. Yamaguchi, R. Tsugami, T. Fujiwara, T. Fukui and S. Narikawa, "FPGA-based ultra-low latency background remover," 2024 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, USA, 2024, pp. 1-2, doi: 10.1109/ICCE59016.2024.10444168.

• T. Kurosawa, Y. Yamaguchi, R. Tsugami, T. Fujiwara, T. Fukui and S. Narikawa, "Low-latency and high-bandwidth communication using HSS transceivers on a Versal FPGA," 2024 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, USA, 2024, pp. 1-2, doi: 10.1109/ICCE59016.2024.10444302.

• Yoshiki Kunimoto, Chang Qiong, Yoshiki Yamaguchi, and Tsutomu Maruyama, ”GPU Acceleration of Multi-object Tracking with Motion Vector interpolation and Affine Transformation,” ASAP2023: 34th IEEE International Conference on Application-specific Systems, Architectures and Processors, pp. 127-134, 2023, doi: 10.1109/ASAP57973.2023.00031.

• Riadh Ben Abdelhamid, Gen Kuwazawa, and Yoshiki Yamaguchi, ”Quantitative study of floating-point precision on modern FPGAs,” HEART2023: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 6 pages, 2023.

• Yoon Jongkwan, Yoshiki Yamaguchi, Yowichi Fujita, Yoshinori Fukao, Eitaro Hamada, Youichi Igarashi, Tetsuichi Kishishita, and Masayoshi Shoji, ”FPGA-based detector with SiC sensing for real-time monitoring of muon beams: A preliminary report of SCIBER-1 in the COMET Phase-α,” HEART2023: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 6 pages, 2023.

• Ryohei Kobayashi, Norihisa Fujita, Yoshiki Yamaguchi, Taisuke Boku, Kohji Yoshikawa, Makito Abe, and Masayuki Umemura, “Accelerating Radiative Transfer Simulation on NVIDIA GPUs with OpenACC,” PDCAT2022: Parallel and Distributed Computing, Applications and Technologies, p.344-358, 2023. doi:10.1007/978-3-031-29927-8 27

• Ryohei Kobayashi, Norihisa Fujita, Yoshiki Yamaguchi, Taisuke Boku, Kohji Yoshikawa, Makito Abe, Masayuki Umemura, “GPUFPGA-accelerated Radiative Transfer Simulation with Inter-FPGA Communication,” HPC Asia ’23: Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, p.117-125, 2023. doi:10.1145/3578178.3578231

• Riadh Ben Abdelhamid and Yoshiki Yamaguchi, “Packed SIMD Vectorization of the DRAGON2-CB,” 2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, pp.85-92, 2022. doi: 10.1109/MCSoC57363.2022.00023.

• Kazuki Furukawa, Tomoya Yokono, Yoshiki Yamaguchi, Kohji Yoshikawa, Norihisa Fujita, Ryohei Kobayashi, Taisuke Boku, and Masayuki Umemura, ``An Efficient RTL Buffering Scheme for an FPGA-Accelerated Simulation of Diffuse Radiative Transfer'', 2021 International Conference on Field-Programmable Technology,  pp. 1-9, 2021, doi: 10.1109/ICFPT52863.2021.9609944.

• Iman Firmansyah and Yoshiki Yamaguchi, ``FPGA-based Implementation of the Stereo Matching Algorithm using High-Level Synthesis", 2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, pp. 1-7, 2021, doi: 10.1109/MCSoC51149.2021.00009.

• Ryo Nakagawa and Yoshiki Yamaguchi, ``Enhanced transplantability for smart agriculture drone by an FPGA with SD standards", Asia Pacific Conference on Robot IoT System Development and Platform, pp.50-54, 2021.

• Yutaka Shinkai and Yoshiki Yamaguchi, ``A Study of Highly Accurate Calibration based on Multiple 6-axis IMUs", Asia Pacific Conference on Robot IoT System Development and Platform, pp.75-81, 2021.

• Naoya Umezu, Yoshiki Yamaguchi, and Taisuke Boku, ``An FPGA-based storage control with load balancing", 2021 IEEE International Conference on Cluster Computing, pp. 791-794, 2021, doi: 10.1109/Cluster48925.2021.00118.

• Norihisa Fujita, Ryohei Kobayashi, Yoshiki Yamaguchi, Taisuke Boku, Kohji Yoshikawa, Makito Abe, and Masayuki Umemura, ``OpenCL-enabled Parallel Raytracing for Astrophysical Application on Multiple FPGAs with Optical Links'', 2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC), pp.48-55, doi: 10.1109/H2RC51942.2020.00011, November 2020.

• Ruochong FAN and Yoshiki YAMAGUCHI,``A study of FPGA-based cluster computing by high-speed serial-link communication'', 2020 Eighth International Symposium on Computing and Networking Workshops, pp.401-405, doi: 10.1109/CANDARW51189.2020.00082, November 2020.

• Norihisa Fujita, Ryohei Kobayashi, Yoshiki Yamaguchi, Kohji Yoshikawa, Makito Abe, and Masayuki Umemura, ``Toward OpenACC-enabled GPU-FPGA Accelerated Computing'', 2020 IEEE International Conference on Cluster Computing, pp.422-423, doi: 10.1109/CLUSTER49012.2020.00060, September 2020.

• Ryohei Kobayashi, Norihisa Fujita, Yoshiki Yamaguchi, Taisuke Boku, Kohji Yoshikawa, Makito Abe, and Masayuki Umemura, ``Accelerating Radiative Transfer Simulation with GPU-FPGA Cooperative Computation'', 2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors, pp.9-16, doi: 10.1109/ASAP49362.2020.00011, July 2020.

• Riadh Ben Abdelhamid, Yoshiki Yamaguchi, and Taisuke Boku, ``Condensing an overload of parallel computing ingredients into a single architecture recipe'', 2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors, pp. 25-28, doi: 10.1109/ASAP49362.2020.00013, July 2020. 

• Norihisa Fujita, Ryohei Kobayashi, Yoshiki Yamaguchi, Tomohiro Ueno, Kentaro Sano, and Taisuke Boku, ``Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA'', 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, pp.450-459, doi: 10.1109/IPDPSW50202.2020.00083., May 2020.

• Changdao Du, Iman Firmansyah, and Yoshiki Yamaguchi, ``High-Performance Computation of LGCA Fluid Dynamics on an FPGA-based Platform'', The 5th International Conference on Computer and Communication Systems, pp.520-525, doi: 10.1109/ICCCS49078.2020.9118557, May 2020.

• Riadh Ben Abdelhamid and Yoshiki Yamaguchi, ``A block-based systolic array on an HBM FPGA for DNA sequence alignment'', The 16th International Symposium on Applied Reconfigurable Computing, doi: 10.1007/978-3-030-44534-8_23, pp.298-313, March 2020.

• Changdao Du, Iman Firmansyah and Yoshiki Yamaguchi, ``FPGA-Based Computational Fluid Dynamics Simulation Architecture via High-Level Synthesis Design Method'', The 16th International Symposium on Applied Reconfigurable Computing, pp.232-246, doi: 10.1007/978-3-030-44534-8_18, March 2020.

• Ryohei Kobayashi, Norihisa  Fujita, Yoshiki  Yamaguchi, Ayumi Nakamichi, and Taisuke Boku, ``OpenCL-enabled GPU-FPGA Accelerated Computing with Inter-FPGA Communication'', The International Conference on High Performance Computing in Asia-Pacific Region Workshops,pp.17-20, January 2020.

• Mirai Niki, Yoshiki Yamaguchi, and Toshiyuki Amagasa, ``FPGA-based SPARQL query acceleration'', Asia Pacific Conference on Robot IoT System Development and Platform, Extended Abstract of ESS,(23) 1-2, November 2019.

• Yuji Nagaoka and Yoshiki Yamaguchi, ``FPGA-based low latency framework for Vehicle-to-Vehicle wireless communication'', Asia Pacific Conference on Robot IoT System Development and Platform, Extended Abstract of ESS,(22) 1-2, November 2019.

• Riadh Ben Abdelhamid, Yoshiki Yamaguchi, and Taisuke Boku, ``MITRACA, a next-gen heterogeneous architecture for scientific computing'', IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip,pp.304-311, October 2019.

• Norihisa Fujita, Ryohei Kobayashi, Yoshiki Yamaguchi, and Taisuke Boku, ``Parallel Processing on FPGA Combining Computation and Communication in OpenCL Programming'', The Ninth International Workshop on Accelerators and Hybrid Exascale Systems,pp.479-488, July 2019.

• Ryohei Kobayashi, Norihisa Fujita, Yoshiki Yamaguchi, Ayumi Nakamichi, and Taisuke Boku, ``GPU-FPGA Heterogeneous Computing with OpenCL-Enabled Direct Memory Access'', The Ninth International Workshop on Accelerators and Hybrid Exascale Systems,pp.489-498, July 2019.

• Riadh Ben Abdelhamid, Yoshiki Yamaguchi, and Taisuke Boku, ``MITRACA: Manycore Interlinked Torus Reconfigurable Accelerator Architecture'',2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors,pp.38, July 2019.

• Changdao Du and Yoshiki Yamaguchi, ``A High-Level Synthesis Design for a Scalable Hydrodynamic Simulation on OpenCL FPGA Platform,' 'The 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies,(19) 1-4, June 2019.

• Iman Firmansyah, Du Changdao, Norihisa Fujita, Yoshiki Yamaguchi, and Taisuke Boku, ``FPGA-based Implementation of Memory-Intensive Application using OpenCL'', The 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies,(16) 1-4, June 2019.

• Ryohei Kobayashi, Norihisa Fujita, Yoshiki Yamaguchi, and Taisuke Boku, ``Parallel Processing on FPGA Combining Computation and Communication in OpenCL Programming'',2019 IEEE International Parallel and Distributed Processing Symposium Workshops,pp.479-488, doi: 10.1109/IPDPSW.2019.00089, May 2019.

• Norihisa Fujita, Ryohei Kobayashi, Yoshiki Yamaguchi, Yuma Oobata, Taisuke Boku, Makito Abe, Kohji Yoshikawa, and Masayuki Umemura, ``Accelerating Space Radiate Transfer on FPGA using OpenCL'', International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies,pp.1-7, doi:10.1145/3241793.3241799, June 2018.

• Ryohei Kobayashi, Yuma Oobata, Norihisa Fujita, Yoshiki Yamaguchi, and Taisuke Boku, ``OpenCL-ready High Speed FPGA Network for Reconfigurable High Performance Computing'', HPC Asia 2018, pp.192-201, January 2018.

•  Iman Firmansyah, Yusuf Nur Wijayanto, and Yoshiki Yamaguchi,``2D Stencil Computation on Cyclone V SoC FPGA using OpenCL'',2018 International Conference on Radar, Antenna, Microwave, Electronics, and Telecommunications,pp.121-124, November, 2018.

•  Hiroki Nakamura, Hirotaka Takayama, Yoshiki Yamaguchi, and Taisuke Boku, ``Thorough analysis of PCIe Gen3 Communication'', International Conference on Reconfigurable Computing and FPGAs,pp.1-6., December, 2017.

•  Nakano Masataka and Yamaguchi Yoshiki, ``A Study of TRAX Player by Template Matching'', International Workshop on Advances in Networking and Computing,pp.570-574, November 2017.

•  Chengzhe Li, Hiroshi Maruyama, Lai Yoong Yee, and Yoshiki Yamaguchi, ``FPGA-based Volleyball Player Tracker'', ACM SIGARCH Computer Architecture News, Vol.44, Issue 4, pp.80-85, December, 2016.

•  M. Nakano and Y. Yamaguchi, ``A Study of TRAX Player by Template Matching'', International Workshop on Advances in Networking and Computing,pp.570-574, November, 2017.

• Iman Firmansyah, Yoshiki Yamaguchi, and Taisuke Boku, ``Performance evaluation of Stratix V DE5-Net FPGA board for high performance computing'', The 2016 International Conference on Computer, Control, Informatics and its Applications,pp.23-27, October, 2016.

• Iman Firmansyah, Yoshiki Yamaguchi, and Taisuke Boku, ``Capability assessment of a multiple-FPGA system for high-performance computing'', ISC 2016 HPC in ASIA Posters, June, 2016.

• H. Jin, Y. Yamaguchi and Y. Kodama, ``Efficient shared cache system for ARM-based multi-core processors'', The 5th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART2014),pp.99-102, June, 2014.

• S. Ochiai, Y. Yamaguchi and Y. Kodama, ``The Flexible Sound Synthesizer on an FPGA'', International Symposium on Computing and Networking --Across Practical Development and Theoretical Research-- (CANDAR2013),pp.104-111, Dec. 2013.

• K. Kinoshita, T. Okamura, D. Takano, T. Yao and Y. Yamaguchi, ``Spatiotemporal modular arrangement for energy efficient reconfigurable SoCs'', the IEEE 7th International Symposium on Embedded Multicore System on Chips (MCSoC2013),pp.97-100, Sept. 2013.

• K. Fujinami, Y. Yamaguchi, A. Sugiura and Y. Kodama, ``A Study of a Three-Dimensional Multiphase-Flow Simulator'', The 23rd international conference on field programmable logic and applications (FPL2013),pp.1-4, Sept. 2013.

• T. Yabuki, Y. Yamaguchi, and Y. Kodama, ``Real-time Video Stabilization on an FPGA,'' The IEEE 2013 International Conference on Smart Structures and Systems (ISSS2013),pp.114-1196, Mar. 2013.

• K. Kinoshita, D. Takano, T. Okamura, T. Yao and Y. Yamaguchi, ``An augmented reality system with a coarse-grained reconfigurable device'', ACM SIGARCH CAN, Vol.40, Issue 5, pp.16-21, 2012.

• T. Yabuki, S. Ochiai, Y. Yamaguchi and Y. Kodama,``Connect6 Game-tree Reduction based on Image Processing and Its Positional Symmetric Property, ''International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2012),pp.159-162, May 2012.

• S. Tanabe, T. Nagashima, and Y. Yamaguchi, ``An Augmented Reality System with Coarse-Grained Device'', ACM SIGARCH CAN Vol.39 Issue 4, pp.86-89, 2011.

• Yoshiki Yamaguchi, Kuen-Hung Tsoi, and Wayne Luk, ``FPGA-based Smith-Waterman Algorithm: Analysis and Novel Design'', Int'l Conf. on Applied Reconfigurable Computing (ARC2011),pp.181-192, Mar. 2011.

• Yoshiki Yamaguchi, Kuen-Hung Tsoi, and Wayne Luk, ``A comparison of FPGAs, GPUs and CPUs for Smith-Waterman algorithm'', Int'l Symp. on Field-Programmable Gate Arrays (FPGA2011), pp.281, Feb. 2011.

• Shuhei Yoshida and Yoshiki Yamaguchi, ``A Study of an FPGA Synthesizer'', Int'l Conf. on Audio, Language and Image Processing (ICALIP2010),pp.1205-1210, Nov. 2010.

• Yusuke Arai, Yoshiki Yamaguchi, Moritoshi Yasunaga, ``FCHC Lattice Gas Model on Playstation3'',Int'l Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2010),pp.131-136, Jun. 2010.

• S. Hiinaga, Y. Yamaguchi, T. Yao, and T. Kawabe, ``Dynamic Reconfiguration System for Real-Time Video Processing'', Int'l Conf. on Field Programmable Logic and Applications (FPL2010),pp.691-694, Aug. 2009.

• S. Asano, T. Maruyama and Y. Yamaguchi, ``Performance Comparison of FPGA, GPU and CPU in Image Processing'', Int'l Conf. on Field Programmable Logic and Applications (FPL2009),pp.126-131, Aug. 2009. 

• A. Kanamaru, H. Kawai, Y. Yamaguchi, M. Yasunaga, ``Tile-Based Fault-Tolerant Approach using Partial Reconfiguration'', Int'l WS on Applied Reconfigurable Computing (ARC2009),pp.293-299, Mar. 2009.

• Y. Arai, Y. Yamaguchi, T. Maruyama, and M. Yasunaga, ``Experience of Lattice Gas Automata Simulator -- toward large-scale PlayStation 3 cluster --'',Parallel and Distributed Computing and Networks 2009 (PDCN2009),pp.181-188, Feb. 2009.

• H. Kawai, Y. Yamaguchi, M. Yasunaga, K. Glette and J. Torresen, ``A Self-Adaptive Pattern Recognition Hardware with On-chip Partial Reconfiguration'', Int'l Conf. on Field-Programmable Technology 2008 (ICFPT'08),pp.169-176, Dec. 2008.

• T. Saegusa, T. Maruyama, and Y. Yamaguchi, ``How fast is an FPGA in image processing?'',18th Int'l Conf. on Field-Programmable Logic and Applications (FPL2008),pp.77-82, Sep. 2008.

• Y. Yamaguchi, N. Aibe, M. Yasunaga, Y. Yamamoto, T. Awano, and Ikuo Yoshihara, ``Bio-Inspired Functional Asymmetry Camera System'', Int'l Conf. on Neural Information Processing (ICONIP2007),pp.637-646, Nov. 2007.

• Y. Arai, R. Sawai, Y. Yamaguchi, T. Maruyama, and M. Yasunaga, ``A Lattice Gas Cellular Automata Simulator with Cell Broadband Engine'', Parallel Computing 2007 (ParCo2007),pp.459-466, Sep. 2007.

• Y. Yamaguchi, T. Maruyama, F. Konoshi, and A. Konagaya, ``High speed tabulation system using an FPGA designed for distribution tables of frequent DNA subsequences'',17th Int'l Conf. on Field-Programmable Logic and Applications (FPL2007),pp.145-150, Aug. 2007.

• S. Masuno, T. Maruyama, Y. Yamaguchi, and A. Konagaya, ``An FPGA Implementation of Multiple Sequence Alignment Based on Carrillo-Lipman Method'',17th Int'l Conf. on Field-Programmable Logic and Applications (FPL2007),pp.489-492, Aug. 2007.

• Y. Yamaguchi, K. Kanazawa, Y. Ohke and T. Maruyama, ``An acceleration method for evolutionary systems based on iterated prisoner's dilemma'', International Workshop on Applied Reconfigurable Computing (ARC2007), pp.358-364, Mar. 2007.

• H. Kawai, Y. Yamaguchi, and M. Yasunaga, ``Realization of the sound space environment for the radiation-tolerant space craft'', the 3rd International Conference on ReConFigurable Computing and FPGAs (ReConFig2006), pp.198-205, Sep. 2006.

• S. Masuno, T. Maruyama, Y. Yamaguchi, A. Konagaya, ``Multidimensional Dynamic Programming for Homology Search on Distributed Systems'', European Conference on Parallel Computing (Euro-Par2006), pp.1127-1137, Sep. 2006.

• H. Kawai, Y. Yamaguchi, and M. Yasunaga, ``Improvement of module redundancy using FPGA'', 6th European Workshop on Microelectronics Education (EWME2006), pp.67-70, Jun. 2006. 

• K. Glette, J. Torresen, Y. Yamaguchi, and M. Yasunaga, ``On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition'', First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), pp.373-380, Jun. 2006. 

• Y. Yamaguchi, T. Maruyama, R. Azuma. and A. Konagaya, ``Spatiotemporal Simulation of a Single Living Cell'', IEEE 2005 Conference on Field-Programmable Technology (ICFPT'05),pp.267-274, Dec. 2005.

• S. Masuno, T. Maruyama, Y. Yamaguchi, and A. Konagaya, ``Multidimensional Dynamic Programming for Homology Search'',15th International Conference on Field Programmable Logic and Applications (FPL2005),pp.173-178, Aug. 2005.

• R. Azuma, Y. Yamaguchi, T. Kitagawa, T. Yamamoto, and A. Konagaya, ``Mesoscopic simulation method for spatio-temporal dynamics under molecular interactions'', HUGO's 10th Human Genome Meeting (HGM2005),WOS5-036/WPS5-070, Apr. 2005. 

• Y. Yamaguchi, T. Maruyama, and A. Konagaya, ``Three-dimensional dynamic programming for homology search,''14th International Conference on Field Programmable Logic and Applications (FPL2004),pp.505-515, Aug. 2004.

• Y. Yamaguchi, R. Azuma, and A. Konagaya, ``An approach for high speed Monte Carlo simulation with FPGA --toward a whole cell simulation--'',46th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2003),No.386B(1-4), Dec. 2003. 

• Y. Yamaguchi, Y. Miyajima, T. Maruyama, A. Konagaya, ``High Speed Homology Search with Run-time Reconfiguration,''12th International Conference on Field-Programmable Logic and Applications (FPL2002),pp.281-291. Sep. 2002.

• Y. Yamaguchi, T. Maruyama, and A. Konagaya, ``High Speed Homology Search with FPGAs, ''Pacific Symposium on Biocomputing 2002 (PSB2002), pp.271-282, Jan. 2002. Y. Yamaguchi, T. Maruyama, and A. Konagaya, ``An Approach for High Speed Homology Search with FPGAs,`` 5th International Conference on Knowledge-Based Intelligent Information Engineering Systems & Allied Technologies (KES'2001),pp.783-787, Se. 2001.

• T. Maruyama, Y. Yamaguchi, and A. Kawase, ``An Approach to Real-Time Visualization of PIV Method with FPGA,''11th International Conference on Field-Programmable Logic and Applications (FPL2001),pp.601-606, Aug. 2001.

• Y. Yamaguchi, A. Miyashita, T. Maruyama, and T. Hoshino, ``A Co-processor System with a Virtex FPGA for Evolutionary Computation,''10th International Conference on Field-Programmable Logic and Applications (FPL2000),pp.240-249, Aug. 2000.

• Y. Yamaguchi, T. Maruyama, and T. Hoshino, ``A Co-evolution Model of Scores and Strategies in IPD games --toward the understanding of the emergence of the social morals--,''7th International Conference on Artificial Life (ALIFE VII),pp.362-366, August 2000.

• Y. Yamaguchi, T. Maruyama, and T. Hoshino, ``High Speed Hardware Computation of Co-evolution Models,''5th European Conference on Artificial Life (ECAL'99),pp.566-574, Sep. 1999. 

• 山口佳樹, "FPGAと分散型システム：「The Network is the Computer」を再考する", CS特別招待講演2, 信学技報, vol. 124, no. 416, CS2024-103, pp. 73-73, 2025年3月.

• Y. Yamaguchi, "Beyond Programmability: The Future of FPGA Development in a Multifarious", Invited Talk 4, The International Symposium on Microelectronic Engineering & Design 2024 (isMED2024), George Town, Penang, Malaysia, 2 December 2024.

• FTQCアーキテクチャ研究をはじめよう！（モデレータ：天野英晴(東大)．パネリスト：北川勝浩(阪大)、池田誠(東大)、今村智史(富士通)、片桐孝洋(名大)、山口佳樹(筑波大)、Rod Van Meter(慶大)）, 第1回 誤り訂正量子コンピュータアーキテクチャ研究会, 2024年11月．

• Y. Yamaguchi, "Unlocking the Potential of FPGA: Exploring Evolution, Diversity, and Future Directions", Keynote Talk 3, The 2024 International Conference on Radar, Antenna, Microwave, Electronics and Telecommunications (ICRAMET), Online, 13 November 2024.

• 山口佳樹, "FPGA技術の進化と次世代応用への展望", 第18回ACRiウェビナー「さらに広がるFPGAの可能性」, アダプティブコンピューティング研究推進体 (Adaptive Computing Research Initiative, ACRi), 2024年9月27日.

• 山口佳樹, "半導体チップとアーキテクチャの共進化", 筑波大学情報学群情報科学類（オープンキャンパス模擬講義）, 2024年8月3日.

• FPGAクラスタによるHPC/AIの展望（モデレータ：朴泰祐(筑大), パネリスト：佐野健太郎(理研), 竹岡尚三(アックス), 堀江義弘(AMD), 山口佳樹(筑大)）, PC Cluster Consortium HPCオープンソースソフトウェア普及部会, New FPGA era for HPC cluster, 2022年5月．

• Yoshiki Yamaguchi, “What do you need to be successful on your next-generation HPC system?,” IXPUG Birds-of-a-Feather of Achieving Performance on Current and Future Large-Scale Intel Xeon-Based Systems in Supercomputing 2019, panel discussion, November 2019.

• 山口佳樹, “FPGA アプリケーションから見た原子スイッチ FPGA”, Non-Volatile Field-Programmable Gate Array Initiative, 2019 年 7 月.

• 山口佳樹，“スポーツ医科学を支援するセンサインテグレーション,” ARIHHP ヒューマン・ハイ・パフォーマンスフォーラム 2019，2019 年 3 月．

• 山口佳樹，“AI とロボットで見直される進化型ハードウェア,” 日本学術振興会 シリコン超集積システム第 165 委員会，第 85 回研究会，2017 年 4 月．

• Yoshiki Yamaguchi, “Hardware Direct Computation for Bioinformatics Applications,” Frontier 8 at AnalytiX2014, 2014 年 4 月.

• 山口佳樹, “書き換え可能 LSI における画像処理 –FPGA による高速化可能性と抱えている問題について,” 豊田中央研究所, 2013年12月.

• Y.Yamaguchi, “High-efficient Computing with Reconfigurable Devices – the comparison of CPUs, GPGPUs, and FPGAs,” the University of Edinburgh, Aug. 2012．

• Y.Yamaguchi, “High-efficient Computing with Reconfigurable Devices,” IEEE Singapore Section (National University of Singapore), Dec. 2010．

• 山口佳樹, “Cell/B.E. を用いた高速計算について,” FAIS マルチコア Workshop2009，福岡， 2009 年 10 月．

• 山口佳樹, “応用事例から眺める書き換え可能性の可能性”, 次世代 RHW 創造研究会, 宮城, 2009 年 10 月.

• 山口佳樹，“FPGA を利用したシステム構築について,” 第 42 回 超並列計算研究会，東京， 2005 年 11 月．

• 山口佳樹, "半導体集積回路の成長と進化―CPU，GPU，FPGA―", 電子情報通信学会誌（知識ベース・知識の森）, Vol.107, No.10, pp.988-990, 2024年10月.

• 丸山勉，山口佳樹，長名保範，“FPGA 原理和”, 第 7 章 PLD/FPGA 用案例, 人民出版社, pp.198-236, 2019年 3 月．

• Tsutomu Maruyama, Yoshiki Yamaguchi, Yasunori Osana, “Programmable Logic Devices (PLDs) in Practical Applications”, Chapter 7 in Principles and Structures of FPGAs, p.179-205, Springer, Sep. 2018.

• 丸山勉，山口佳樹，長名保範，“7 章 PLD/FPGA の応用事例” in FPGA の原理と構成, p.209-245, オーム社, 2016 年 4 月．

• Y. Yamaguchi, Y. Osana, M. Yoshimi, and H. Amano, “FPGA-based HPRC for Bioinformatics Applications”, Chapter 5 in High-Performance Computing Using FPGAs, p.137-175, Springer, Mar. 2013.

• 山口佳樹, “高速な画像検出回路を実現する", ディジタル・デザイン・テクノロジ, CQ 出版, pp.77-88, 2012年 10 月．

• 堀洋平，川合浩之，山口佳樹, “FPGA の部分再構成の今とこれから ～部分再構成の利点と応用へのヒント”，Design Wave Magazine，CQ 出版， pp.129-135， 2007 年 9 月